High level synthesis of timed asynchronous circuits

T. Yoneda, A. Matsumoto, M. Kato, C. Myers
March 2005
DOI

Abstract

This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthesis is used to allow for global and timing optimization. In order to reduce the overhead in resetting phases, a protocol called early acknowledgment protocol and its STG (signal transition graph) generation technique are proposed. In this protocol, the state variables inserted to guarantee that STGs have CSC (complete state coding) usually cause no overhead. The experiments to synthesize a portion of a DCT circuit show that the proposed method can handle a nontrivial example and produce a smaller and faster circuit than a previous approach.

Type
Conference paper
Publication
11th IEEE International Symposium on Asynchronous Circuits and Systems
asynchronous circuits asynchronous circuit high level synthesis state-space methods asynchronous gate-level circuits complete state coding CSC DCT circuit Discrete cosine transforms early acknowledgment protocol global optimization logic synthesis resetting phase overhead resource allocation/scheduling signal transition graph SpecC SpecC specifications specification languages state-based logic synthesis STG generation timed asynchronous circuits timed STGs timing timing optimization logic circuits signal synthesis petri nets protocols circuit circuit synthesis circuit optimization informatics

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